6 channels of audio?

Someone recently asked about if 6 channels of audio would be possible with the Tympan.

The short answer is that, no, the Tympan does not currently support that many channels. The basic Tympan supports two channels in and two channels out. If you buy an AIC shield or an Earpiece shield, that adds two more channels and gets you up to 4 inputs and 4 outputs. That’s what Tympan supports.


While it is true that, right now, the Tympan only supports up to 4 channels, it may be possible to hack the system to add yet another AIC shield in order to get 6 channels in and 6 channels out. Below is my idea for how such a hack might work. I do not know if this idea actually works; it’s just an idea.

Not for Tympan RevD: This idea will definitely not work for Tympan RevD as this hack requires capabilities of the Teensy 4.1. The T4.1 is the heart of the Tympan RevE. So, we need a Tympan RevE (or later?).

Use Multiple I2S Channels: This idea requires that we use the expanded I2S communication capabilities of the Teensy 4.1. The T4.1 has lots of options. We could use the additional I2S busses of the T4.1, or we could use the additional I2S channels of the main I2S bus. I would focus on the latter approach…using additional I2S channels of the main bus. This would be most similar to how we have already implemented the 4-in/4-out version of Tympan. That configuration uses two I2S channels on the main I2S bus. For this hack, we would simply use the third I2S channel on the main I2S bus.

Given that this is just an idea and not yet a solution, there are many things left to figure out:

  • I2S Wiring: An I2S bus is how the digital audio data flows between the audio codec (“AIC”) and the main processor. We would need to look at the T4.1 pinout and see which pins are associated with the third I2S channel on the main I2S bus. The clock lines will all be shared, but we need that third set of I2S data lines. Which T4.1 pins do we attach wires to? How can we fly those wires up to the hypothetical added Tympan AIC shield?

  • I2C Wiring: An I2C bus is how the main processor sends configuration and control messages to the AIC. The 3206AIC used by Tympan is hardwired to a single I2C address, so we cannot have multiple AICs on a single I2C bus (without additional chips to translate). Therefore, if we are adding another Tympan AIC shield, we need to find a third I2C bus on the Teensy. Does the T4.1 have a 3rd I2C bus? Which pins? Can we fly wires from those pins up to the added AIC shield?

  • Firmware: I do believe that the Teensy Audio library already supports the multiple I2S busses of the T4.1 (see AudioIinptuI2S2) and the additional I2S channels of the main bus (see AudioInputI2SHex and AudioInputI2SOct). For this hack, I’d focus on AudioInputI2SHex because it would be most similar to AudioInputI2Squad that we’re already using for the 4-in/4-out Tympan. After wiring up the I2S and I2C connections, we’d test using the Teensy version of AudioInputI2SHex just to prove that it all works. Then, we would look make a Tympan version of AudioInputI2SHex. Or, we could stay with the Teensy library version of it as-is, but we’d have to give up the ability to change sample rate and audio block size, which is maybe OK.

Phew. Sounds like lots of work…but I’m kinda excited at the thought!

Here is the Teensy 4.1 pin map, however, not all alternate pin functions are listed. Refer to the NXP processor’s reference manual for a complete list (pg 309).

The Teensy 4.1 does have (3) I2C channels exposed, but SDA2/SCL2 may not be exposed on the Tympan’s header. In that case, one may need to fly two wires from the Teensy to the new shield.

The Teensy 4.1 documentation only lists (2) I2S port. The processor has (3) I2S pots, but only (2) are exposed as pins on the Teensy.

Here are exposed Teensy pins for the I2S Data Rx (audio data into the processor):

SAI-1 (Data Rx)

  • GPIO_B1_00 (Pin-8): SAI1_RX_DATA0
  • GPIO_B0_10 (Pin-6): SAI1_TX_DATA3 and SAI1_RX_DATA1
  • GPIO_B0_11 (Pin-9) SAI1 _TX_DATA2 and SAI1_RX_DATA2
  • GPIO_SD_B1_02 (No)
  • GPIO_SD_B1_01 (No)
  • GPIO_SD_B1_00 (No)
  • GPIO_AD_B1_12 (Pin-38) SAI1_RX_DATA0 GPIO_B1_00
  • GPIO_SD_B1_06 (Used for SD card)

SAI-2 (Data Rx)

  • GPIO_AD_B0_08
  • GPIO_EMC_08 (Pin-5)

SAI-2 (Data Rx)

  • GPIO_EMC_33 (No)
  • GPIO_SD_B1_00 (No)

In Summary, you can only access (2) I2S ports on the Teensy 4.1. However, as Chip points out in a later post, one could run the first I2S port with four channel audio (Quad I2S)

For reference, here is a timing diagram of the I2S port


I’m not sure that the pinmap tells the whole story. If my memory serves, some of the I2S output pins can be configured as I2S inputs instead. Crazy! if so, that might explain why it looks like there are 4 output ports but only 2 input ports.

So, I think that one would have to look at the docs for AudioInputI2SHex to see which pins they use. I mean, they wrote the class, so there must be a way to get it to work!

Also, it looks like the whole 2nd I2S bus is available via Teensy Pins 2-5. So, even if we’ve already used the pins assumed by AudioInputI2SHex, maybe we still have Pins 2-5 available? (If so, we would use AudioIinptuI2S2 instead of AudioIinptuI2SHex)



Per the Teensy Audio Design Tool, it looks like AudioInputI2SHex calls for these pins…


And AudioOutputI2SHex calls for these pins…


Do we have these pins available?

(If not, we could also look at AudioInputI2SOct and AudioOutputI2SOct, as maybe we have the 4th I2S port open to us and we’d simply ignore the 3rd I2S port.)

Chip, I revised my post above. The pins you listed are all alternates for the 1st I2S Port. Only (2) I2S ports are exposed to the Tympan.

Revised as Chip pointed out that each I2S port contains 3 independent In/Out data pairs. See posts below.


I think that we’re talking past each other a bit here. I agree that the T4.1 only exposes two I2S ports. But, on that first I2S port, there are multiple data lines available. They can be used in parallel, not just as alternatives to each other.

This is how the existing I2SQuad class works, for example. Both AICs are on one I2S port. They both share the same three clock lines, but each AIC is provided its own RX and TX data lines.

As you noted, the NXP documentation is tricky here as many of these data lines can be used as either RX or as TX, or can even be substituted for each other. Also as you noted, yet another complication is trying to figure out which of these lines are broken out to pins on the T4.1.

According to the Teensy docs for the T4.1, here’s what I see.


In this table, you can see that sometimes pins are used as inputs and sometimes as outputs. In the end, they only appear to have exposed 5 data pins, which means that you can’t max out the system with 8-in / 8-out and, instead, you have to trade inputs and outputs to achieve your goal. Based on how they’ve carefully chosen to re-use the pins, there appear to be several options for us, but the most useful might be:

  • 3 AICs for inputs and 2 AICs for output, which yields 6 audio inputs and 4 audio outputs

For this case, it looks like we’d use pins 8 (RX), 7 (TX), 6 (RX), 32 (TX) which is just like our normal “quad” setup…and then we’d send pin 9 to the 3rd AIC to provide the extra RX channels. The outputs of the 3rd AIC would be unused. We would then use AudioInputI2SHex for our inputs and AudioOutputI2SQuad for our outputs. We’d hope that they play nicely together.

Follow Up Note: Looking at the schematic for the Tympan RevE, I now see that Pin 9 is already used. It’s the reset pin for the Bluetooth module. So, if one wanted to use the Tympan’s bluetooth module along with the hack above, it wouldn’t work.

I believe that you suggested an alternative approach that would also work: break out the 3rd I2S port. In this scenario, each AIC would be on its own I2S port, which does give it some advantages.

It’s main advantage is that it would give us full RX and TX to all three AICs, which means all 6 audio channels as inputs and all 6 audio channels as outputs. A secondary advantage is that it is more flexible because each port (and, therefore, each AIC) can be clocked independently, allowing them to be run at different sample rates. Snazzy!

The downside with this approach is that (I believe) we would also need to break out the clock lines associated with each I2S port. With three ports, that’s a lot of lines to break out. It’s annoying for the PCB layout given the limited area under the processor IC, but surely it’s do-able:


For firmware, I see that the Teensy Audio library does support the first I2S port (via AudioInputI2S and AudioOutputI2S) and the second I2S port (via AudioInputI2S2 and AudioOutputI2S2). Sadly, I do not see any support for the 3rd I2S port. Presumably, using the first two as a model, we could add support for the 3rd fairly easily.

Follow-Up Note: Looking at the schematic for the Tympan RevE, I now see that the pins for the second I2S port (pins 2,3,4,5) are already used on the RevE. These are used the Bluetooth module. So, we probably can’t use I2S2. But, we might be able to use I2S3, if they were broken out from the processor IC.

Thank you for pointing that out. I did not realize that each SAI peripheral offered three independent data pairs. But as you showed, setting up quad I2S uses pins from a single SAI port. That’s great!

As for the I2C Wiring, maybe this is a solution: TCA9548, a Low-Voltage 8-Channel I2C Switch.

Another idea, at the risk of being all too familiar: the I2C bus of the AIC3206 codec is only addressable when nRESET is set HIGH via pin 31, so that when using multiple codecs, you can activate each of them via the nREST ports. With nRESET = LOW the codec is not visible on the bus lines SDA and SCL, according to my investigations. One would have to spend then simply still another Teensy port for the control of 2 Codecs. In other words: One switches the I2C bus lines of 2 or more codecs in parallel and activates separately the desired codec over a Teensy port determined for it.